In a VDMOS device (FIG. 1) the resistive component due to the JFET area that is created between body wells limits an increase in the packing density, and thus an improvement in the static and dynamic performances of the device. The JFET resistance depends not only on the epitaxial layer resistivity, but also on the distance between the two adjacent body wells. The capacitances associated with the gate oxide, and thus the charge storage capacity of the gate region depend, in an opposite sense, on this distance.
Improving the output resistance by increasing the distance between the body wells means penalizing the dynamic features of the device. This problem occurred up to now mainly in high voltage MOS devices (˜500V) because of the high epitaxial layer resistivity (˜20Ω/cm), while in low voltage devices (30-60V) the problem is considered almost negligible because of the low epitaxial layer resistivity (<1Ω/cm).
As far as PMOS devices are concerned, particularly low voltage PMOS devices, higher and higher integration densities (i.e., scaling down) and the formation of submicron channel lengths, although obtained with other known technologies, led to a considerable reduction of the output resistance components. This is due to the channel and to a greater focus on the component due to the JFET and to the need to reduce capacitances.
By way of example of this trend, the following TABLE 1 shows a comparison between the relative weight of the output resistance components of a 30-volt P-channel device.
TABLE 1Output resistance components for a 30-Relativevolt P-channel PMOS deviceweightDie-package connection25%Substrate contribution12%Epi layer contribution12%Contribution of the JFET between body33%wellsComponent due to the channel18%Ron100% 
To preserve the dynamic features of a PMOS device, and improve in parallel the output resistance thereof, methods based on the reduction of the distance between body wells have been implemented. These prior art methods essentially provide either the surface resistivity modification (FIG. 2) or the following technology change: a) surface enrichment between body wells to locally reduce resistivity (U.S. Pat. Nos. 4,376,286 and 4,974,059); b) use of a low-resistivity surface epitaxial layer; and c) use of trench technology.
The methods a) and b) applied to low voltage PMOS devices involve known technical drawbacks linked to the influence of the enriched layer on the channel. In fact, in a low voltage PMOS structure the drain is characterized by an epitaxial layer whose concentration ranges between 1 and 5*1016 at/cm3, and gate oxides, because of the low threshold voltage (driving with Vg<4.5V) and the low capacitances required by the applications, have a thickness not lower than 200 Å and peak concentrations in the channel do not exceed 1017 at /cm3.
This means that the highest concentration in the channel is higher by almost an order of magnitude than the epitaxial layer concentration (FIG. 3). Consequently, as soon as attempts are made to enrich uniformly the whole surface, channel features (e.g., threshold voltage and channel length) are significantly changed which jeopardizes function of the PMOS device. This phenomenon is known as premature punch through.
With the third mentioned method, point (c), the JFET component can be eliminated. However, the capacitance problem is not solved since in most cases the area whereon the gate oxide rests is increased, as shown by the comparison between the two gate structures represented in FIG. 4. In the case of a planar structure VDMOS the gate area is proportional to the distance L (1.5-4 μm), while in the case of a trench technology device it is proportional to the sum of the double depth and of the trench width (2h+1˜2.5-4 μm).